1. Technical Field
The present disclosure relates to Radio Frequency (RF) circuit components, and more particularly, to a zero insertion loss directional coupler for wireless transceivers with integrated power amplifiers.
2. Related Art
Generally, wireless communications involve a radio frequency (RF) carrier signal that is variously modulated to represent data, and the modulation, transmission, receipt, and demodulation of the signal conform to a set of standards for coordination of the same. Many different mobile communication technologies or air interfaces exist, including GSM (Global System for Mobile Communications), EDGE (Enhanced Data rates for GSM Evolution), and UMTS (Universal Mobile Telecommunications System). More recently, 4G (fourth generation) technologies such as LTE (Long Term Evolution), which is based on the earlier GSM and UMTS standards, are being deployed. Besides mobile communications modalities such as these, various communications devices incorporate local area data networking modalities such as Wireless LAN (WLAN)/WiFi, ZigBee, and so forth.
A fundamental component of any wireless communications system is the transceiver, that is, the combined transmitter and receiver circuitry. The transceiver encodes the data to a baseband signal and modulates it with an RF carrier signal. Upon receipt, the transceiver down-converts the RF signal, demodulates the baseband signal, and decodes the data represented by the baseband signal. An antenna connected to the transmitter converts the electrical signals to electromagnetic waves, and an antenna connected to the receiver converts the electromagnetic waves back to electrical signals. Depending on the particulars of the communications modality, single or multiple antennas may be utilized. The transmitter typically includes a power amplifier, which amplifies the RF signals prior to transmission via an antenna. The receiver is typically coupled to an antenna and includes a low noise amplifier, which receives inbound RF signals via the antenna and amplifies them.
The power amplifier is a key building block in all RF transmitter circuits. To lower the cost and allow full integration of a complete multi-mode multi-band radio frequency System-on-Chip (RF-SoC), integrating the power amplifier with the transceiver circuit is common. Because of advances in nanometer technology, and ever increasing device unity power gain frequency fmax, Radio Frequency Complementary Metal-oxide Semiconductor (RF-CMOS) has become a viable low-cost option for implementing highly integrated Radio Frequency Integrated Circuit (RFIC) products or applications, such as the aforementioned WiFi and 3G/4G LTE applications, as well as point-to-point radio, 60 GHz band Wireless Gigabit Alliance (WiGig), and automotive radar RF-SoC applications. There are challenges associated with the design and fabrication of the power amplifier with a CMOS process, due to high output linear power and corresponding efficiency parameters, along with an extremely low error vector magnitude (EVM) floor requirement. It is understood that the higher the output power, the lower the optimal drain impedance. Thus, resistive loss at the output matching network becomes more significant. Along these lines, shrinking die sizes and the concomitant use of wafer-level chip scale packaging (WLCSP), wafer level ball grid array (WLBGA), and the like have also represented design challenges of RF-SoC devices.
Detecting and controlling the performance of a power amplifier makes it possible to maximize the output power while achieving optimum linearity and efficiency. One conventional technique involves the use of a capacitor to tap a fraction of the output power and feeding the same to a power detector circuit. The performance is highly variable as dependent on the frequency of the signal, temperature, and antenna voltage standing wave ratio (VSWR). Furthermore, without an isolation port, existing techniques involving the application of a complex impedance termination to offset a non-ideal RF port reflection coefficient and non-ideal coupler directivity for minimizing output power variation under VSWR would not be possible. Moreover, accurate power control with a mismatched load in the transmit chain with over 40 dB of dynamic range is also understood to be challenging. Another conventional technique is the use of an edge-coupled transformer at the output of the RF signal chain. Two terminals of the transformer are connected to the main signal path, with the third terminal serving as a detector port, and a fourth terminal serving as an isolation port.
Directional couplers, which are passive devices utilized to couple a part of the transmission power on one signal path to another signal path by a predefined amount, may also be used in multiple wireless systems for such power detection and control. Conventionally, this is achieved by placing the two signal paths in close physical proximity to each other, such that the energy passing through one is passed to the other. This property is useful for a number of different applications, including power monitoring and control, testing and measurements, and so forth.
A conventional directional coupler is a four-port device including an input port (P1), an output port (P2), an isolation port (P3), and a coupled port (P4). The power supplied to the input port P1 is coupled to the coupled port P4 according to a coupling factor that corresponds to the fraction of the input power that is passed to the coupled port P4. The remainder of the power on the input port P1 is delivered to the antenna port P2, and in an ideal case, no power is delivered to the isolation port P3. In actual implementation, however, some level of the signal is passed to both to the isolation port P3 and the coupled port P4, though the addition of an isolating resistor to the isolation P3 may dissipate some of this power. The insertion loss associated with the circuitry between the output of the power amplifier and the antenna, a substantial portion of which is attributable to the directional coupler, represents another challenge in RF-SoC designs.
Various solutions to reduce signal loss in directional couplers have been proposed. One solution disclosed in U.S. Pat. No. 7,446,626 is understood to be directed to coupled inductors with low inductance values. However, the lumped element capacitors utilized therein may be limited, and capable of sustaining a limited voltage level. Another proposal is disclosed in U.S. Pat. No. 8,928,428, where compensation capacitors allow for high voltage operation. Further improvements to directional couplers are disclosed in a pending and commonly owned U.S. patent application Ser. No. 14/251,197 entitled MINIATURE RADIO FREQUENCY DIRECTIONAL COUPLER FOR CELLULAR APPLICATIONS filed on Apr. 11, 2014, the entirety of the disclosure of which is hereby incorporated by reference. Two chains of inductors and two or more compensation capacitors can be used, allowing for high power levels partially because of higher breakdown voltages of the constituent components. Insertion loss may also be minimized because of the small values of the coupled inductors and the reduced loss from the compensation capacitors. However, it would be desirable for insertion loss to be further reduced to a near-zero level.
Accordingly, there is a need in the art for improved directional couplers capable of high operating voltages, zero insertion loss and a miniaturized size for wireless transceivers with integrated power amplifiers.